Apparatus for correcting two groups of multiple errors

ABSTRACT

Apparatus including a decoder adapted for recovering the data from a received message corresponding to the sent message but which may be in error wherein the blocks of data consist of k bytes of data (D0, D1, D2,...Dk-1) each of b bits. The sent message comprises the k bytes of data plus two check bytes C1 and C2, each of b bits. The decoder is effective in recovering the data without error when not more than two of the bytes are in error no matter how many bits may be in error in the two bytes. Pointers are required which indicate the two bytes containing errors. In the absence of the pointers or in the presence of a single false pointer, the decoder is effective in recovering the data without error when not more than a single byte is in error no matter how many bits may be in error in the single byte. The message is encoded by computing the check bytes according to the relationship:

United States Patent Bossen [451 Oct. 10,1972

154] APPARATUS FOR CORRECTING TWO GROUPS OF MULTIPLE ERRORS Wappingers340/1461 AG, 14 .1 AV

[56] References Cited UNITED STATES PATENTS 3,478,313 11/1969 Srinivasan..340/l46.l 3,562,709 2/1971 Srinivasan ..340/146.1 3,582,878 6/1971Bossen ..340/146.1 3,601,798 8/1971 Hsiao ..340/146.1

Primary Examiner-Charles E. Atkinson Attorney-Hanifin and Jancin andHarold H. Sweeney, Jr.

57 ABSTRACT Apparatus including a decoder adapted for recovering thedata from a received message corresponding to the sent message but whichmay be in error wherein the blocks of data consist of k bytes of data (DD,, D ,...D,, each of b bits. The sent message comprises the k bytesofdaiapliis tivo cficfbytes C} andC each of b bits. The decoder iseffective in recovering the data without error when not more than two ofthe bytes are in error no matter how many bits may be in error in thetwo bytes. Pointers are required which indicate the two bytes containingerrors. In the absence of the pointers or in the presence of a singlefalse pointerjthe decoder is effective in recovering the data withouterror when not more than a single byte is in error no matter how manyhits may be in error in the single byte. The message is encoded bycomputing the check bytes according to the relationship:

C1=IDO [D1 IDk 1 C =ID TD 7 D 7* D,,.

wherein I is the identity element and T, T ,...,T"" are distinctnon-zero elements of Galois Field (2") wherein the indicatedmultiplication and addition are the Galois Field defined operations, andwherein b is an integer 1 and k is an integer 2 k 2.

12 Claims, 21 Drawing Figures n' ,0',,--,n' 1C] n' ,o,,---,u' ac'P0,P1,---PKH s s POINTER COMPUTER --10 COMPUTER 12 25 am 1 1 O F' KH Ng-1 2 CONTRO ERROR SIGN/n1 i... COMPUTER GENERATOR l0,--l 1 13. Se a." 20

C "1 S4 l0,l1,"l 1 OR CIRCUITS s g 2s 1 I i o ,o ,---,u I0,I1;-IK-1 i iERROR coRREcToR PATENTEDncr 10 I972 3.697.948 SHEET U10F14 ENCODER MMPROCESSOR M E DECODER DATA )7 SENT RECEIVED RECOVERED MESSAGE MESSAGEFIG. 2

C COMPUTER 10 COMPUTER 12 28 CIRCUITS I 16 2 EPOYPFPKH \A 14 T 1 SIGNALCOMPUTER GENERATORJ ERROR CORRECTOR 132)) ,D ,6 INVENTOR 0' 1' K-DOUGLAS 0. BOSSEN ATTORNEY FIG. 3

PATENTEDocr 10 I972 SHEET USUF 14 FIG. 70

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SHEET 11UF14 FIG. 10b 1 PATENTEDncr 10 I972 SHEET 12 0F 14 AFPARATUS FORCORRECTING TWO GROUPS OF MULTIPLE ERRORS BACKGROUND OF THE INVENTIONThis invention relates to error correcting codes, and more particularly,to an error correcting code which, by the use of pointers, is capable ofcorrecting two bytes of multiple errors.

In data communication systems as well as computers, the information canbe coded by adding redundant bits to the data message in such a way thatthe message can be decoded with a practical amount of apparatus toobtain the original information corrected in the event an error has beenintroduced. Parallel data arrangements, that is, the information iscontained in parallel bytes arranged in a block of data, are used incomputers and are well known especially in multi-channel recordingapparatus. In co-pending application Ser. No. 10,837, filed on Feb. 12,1970, now U.S. Pat. No. 3,629,824 en coding and decoding apparatus isdisclosed in which the redundant or check bits are associated with thedata in a cross byte or cross track direction. This copendingapplication sets forth a code capable of correcting one or more errorswithin a single, multiple-bit byte of data. The data is divided intoblocks which consist of k bytes of data D D, D ,...,D,, (each of bbits), plus two check bytes C and C each of b bits. The decoder iseffective in recovering the data without error when not more than asingle byte of the received message is in error no matter how many bitsmay be in error in the single byte. The present invention utilizes theabove-identified code but extends the capabilities thereof by combiningtherewith pointer signals which extend the error correcting capabilityof the arrangement to two bytes in error regardless of the number ofbits in error in each byte.

SUMMARY OF THE INVENTION It is an object of the present invention toprovide an encoding and decoding system which provides information as towhich bytes are in error and extends the error correcting capabilitiesof the system to two bytes of data in error.

The code has k data byte positions 0, l,...,kl and two check bytepositions k, k 1. Therefore, the whole message has a length k 2, orpositions numbered 0, l 1,...,k 1. In a multi-track tape system, forexample, each block of data has each of its bytes on a different trackso that the code extends across the tracks, each track representing aninformation byte position. The check bytes, when they are generated, areeach placed on further parallel tracks adjacent to the informationtracks. The system generates i and j pointer signals p p,,...,p,,+ wherei represents the track position of the first error signal and jrepresents the track position of the second error signal. Expressedalgebraically,

Each pointer signal is associated with a particular track so that the iand j error signals each designate a particular track, thus indicatingwhich bytes of the multiple bytes are in error.

. Signals referred to as distance" signals d are generated where d, l ji m, which clearly can have values 1, 2,...,k l. The distance signalsrepresent the distance between the i and j error signal bytes. Since thevalues of j-i which are k or k+l indicate an error in one of the checkbytes, and since errors in the check bytes are handled without referenceto the distance signals, the 'set of distance values is restricted tothe set 1, 2, ...,kl that is, d, ,d ,...,d

Single track correction in the random mode is performed in the event ofa non-zero syndrome whether or not there is a single pointer given.Proper correction is accomplished even if a false pointer is providedand there exist errors in a single byte which is not indicated orpointed to. This single track correction is essentially the same singletrack correction set forth in the above identified application Ser. No.10,837. I

The encoder computes the check bytes C and C according to therelationships:

C I D EDT D 69 F 0 63...? wherein I is the identity element and T, F-----I" are distinct, non-zero elements of Galois Field (2), wherein theindicated multiplication and addition are the Galois Field definedoperations, and wherein b is an integer 1, and k is an integer 2 k 2""The decoder computes two expressions known as the syndromes, where D',,,D, ,...,D',,.,, C, C are the received message bytes which may haveerrors in up to two tracks i and j:

S 2 ID' GB TD GB 7 D' 6B...&T"' D' G9C' In the presence of errorpatterns e, and e; in tracks i and siai lbay th a? QQJI Y W Q Theseexpressions can be solved for e, and e, to obtain:

.1t=S1. 1" )Ti( ii 7 and e,=(TJi G91) (T 5 698,). The expressions for e,and e, represent the error pattern in the groups of data or bytes i andj, respectively. The received message data and the error patterns alongwith various control signals can be properly combined to produce thecorrect data D ,I), The symbol refers to the corrected data.

The foregoing and other objects, features and advantages of theinvention will be apparent from the following more particulardescription of a preferred embodiment of the invention, as illustratedin the accompanying drawings.

FIG. 1 shows a block diagram of a data handling system utilizing thepresent invention.

FIG. 2 is an abbreviated data processing flow diagram of a preferredform of the present invention.

FIG. 3 is a schematic diagram showing the organization of the check bitcomputers C and C FIG. 4 is a schematic diagram showing the organizationof the syndrome computers S, and S FIG. 5 illustrates the geometricrelationships of data and check bits of one error correcting code.

FIG. 6 is a schematic diagram showing the details of the pointer latchcircuit of FIG. 2.

FIGS. 7a through 7e are schematic diagrams showing more details of thecontrol signal generator of FIG. 2.

FIG. 8 shows the encoding matrix for the code represented in the checkbit computer mechanization of FIG. 3.

FIG. 9 shows the decoding matrix for the code represented in thesyndrome computer mechanization shown in FIG. 4.

FIG. 10 illustrates that FIGS. 10a, la-l and l0a-2 show more details ofthe mechanization of the error computer of FIG. 2.

FIGS. b and l0b-l show further details of the mechanization of the errorcomputer of FIG. 2.

FIGS. 11 and 11a are a schematic diagram showing in more detail theerror corrector circuits of FIG. 2.

Referring to FIG. I, data enters an encoder 1 through a channel 2.Encoder 1 generates a sent message which passes through channel 3 to aprocessor 4 which performs some operation on the message, for example,storing it and subsequently reactivating it, and then transcribes areceived message which passes through channel 5 to decoder 6 whichdecodes the received message and emits recovered data, which passesthrough channel 7 to some further use. The operation of processor 4 maybe imperfect and make occasional errors so that the received message inchannel S is not necessarily identical with the sent message in channel3. The encoder l and decoder 6 cooperate to emit recovered data atchannel 7 having fewer errors than are made by the processor.

It will be appreciated by those skilled in the art that this inventioncan be applied to information handling systems of various capacities.The invention, will, therefore, be first described in algebraic termswhich are applicable to any size system and subsequently in terms of aspecific system. The symbolism used throughout the application is thestandard Boolean notation where:

= EXCLUSlVE OR AND According to the invention, data is processed by thesystem in blocks consisting of k bytes, each byte having b bits of data.Here and throughout, b designates an integer 1 and k an integer 2 k 2".The values of b and k are to be considered invariant for a particularembodiment, but are variously chosen for embodiments of variouscapacities. A block of data will accordingly be designated D, D,, D vvhere Do represents the first byte in the block, D, the second byte, andso on to D which represents the kth and last byte. A representative byteof data will be designated D, with the subscript j assuming any integralvalue 0 5 j k-l. According to the invention, the encoder calculates fromthe block of data two check bytes, (designated C, and C each of b bitsand appends the check bytes to the k data bytes to generate the sentmessage of k 2 bytes.

In order to describe the calculation of the check bytes, it isconvenient to note that for bytes composed of b binary bits there are 2distinct bytes possible and to regard each possible byte as an elementof a Galois Field of 2 elements (or GF(2") The existence of GF(2 isassured for any value of b by general theorems of algebra. (See forexample, W. Wesley Peterson: Error Correcting Codes, M.l.T. Press,1961). The Galois Filed implies two operations conventionally designatedaddition with the corresponding zero element 0, and multiplication withcorresponding identity element 1. The terms addition and "multiplicationand related terms such as adder will be used in this sense throughout.

The rules of addition and multiplication of bytes are established byrecognizing that the GF(2 of possible bytes is isomorphic with theGF(2") of polynomials with coefficients in GF(2) taken modulo anirreducible polynomial of degree b. At least one irreducible polynomialexists for any b. The field of such polynomials is a vector space ofdimension b over GF(2). Addition of the elements in GF(2) is thereforeaccomplished by addition of corresponding bits. Addition is of course inGF(2) and thus equivalent to addition modulo 2. Multiplication in GF(2)can be thought of as defining a set of linear transformations in thecorresponding vector space of dimension b.

The vector space is spanned by the column vectors:

(wherein the 0 and l are binary symbols), or more compactly expressed:

wherein a is a primitive element of GP (2 (i.e., every non-zero elementof the field can be obtained by raising a to some power.) Thetransformation matrix corresponding to multiplication by element Q isgiven by catenation of the column vectors:

giving:

[TQ= gab-l Q l"'IQ I 1 Multiplication of the element R by the element 0in GF (2") is thus equivalent to multiplication of the vector R by thematrix T where the vector and matrix components are in GF(2). (i.e.,binary bits.) These operations will be illustrated below in connectionwith a preferred embodiment.

Returning now to the data handling system, according to the invention,the encoder calculates the check bytes according to the relationships:

C==ID0 DWMQFI d (5) where T, T ,...,T*" are distinct, non-zero elementsof GF( 2). Since there are 2"-l such elements, the number of bytes in ablock is limited to k 2. It is convenient to express the relationshipsby which C, and C are computed by an encoding matrix given thecoefficients:

and the encoding calculation can be written symbolically:

C H5 D Employing the relationships developed above, the encoding matrixcan be expressed in binary form by replacing each element of GF( 2)appearing in the encoding matrix by the corresponding binarymultiplication matrix. The resulting form of the encoding matrix willgive explicitly the operations to be performed by a binary-basedcomputer to calculate the check bytes.

Turning now to the decoding, the decoder receives a received message:

of k 2 bytes (the symbol refers to the received message) and computes atwo-byte syndrome (8,, 8,) according to the relationships:

l 0 1 2 k-i i S [D 63 T D e37 D',...6BT"" D,, ,BC 9 described by adecoding matrix with k 2 columns and 2 rows:

H I I I I I 0 ITT ...T,, ,9I (10 where 0 is the zero element in GF(2).The calculation of the syndrome can be indicated symbolically:

D( The decoding matrix H can of course be expressed explicitly in binaryform by substituting the binary multiplication matrices.

If I, T, T ,...,T"' are the non-zero elements of GF( 2') then to eachsuch element T, there is an inverse element T" such that TT" I which isthe identity element.

The pointer signals are derived from the system in which the errorcorrection is taking place. For example, each group of data may giverise to a parity check signal which is an indication of the byte of dataassociated therewith being in error. Of course, a parity check bitsignal is produced for each byte of data or group of data, therebyindicating on an individual basis the byte or bytes of data in error. Ofcourse, there are other means of generating pointer" signals such as inset forth in corresponding U.S. patent application Ser. No. 40,836,filed May 26, 1970, entitled Enhanced Error Detection and Correction ForData Systems now U.S. Pat. No. 3,639,900. In this application, the 7quality of the record read back operations on a real time basis is usedas pointers to possible error conditions. The significance of thesyndrome 8,, 8, together with the error pointers P P,,...,P,, can beunderstood from a consideration of the following operations which can bereadily derived from the encoding and decoding relationships on thesupposition that at least all but the two bytes whose pointers areturned on have been correctly transcribed, or that at least all but onebyte of the message have been correctly transcribed in the presence ofno pointers turned on or one pointer turned on. If syndromes S, 0 and S0, then no error exists in the received message, regardless of whetheror not two pointers are turned on. If no pointer or a single pointer isturned on and syndrome S, 0 and S is not equal to 0, then there is anerror C',. If no pointer of one pointer is turned on and syndrome S, isnot equal to 0 and S 0,, then there is an error in C',. If no pointer isturned on or if one pointer is one and S, is not equal to 0 and S, isnot equal to 0, then an error of magnitude S, exists in data byte D, if,and only if, S, T" S,,. Under these conditions, the decoder computes foreach data byte a criterion from the equation 8,, T' S, 69S, andgenerates the recovered data:

D, D, (if S, is not equal to 0) D, D,Q3S, (if 8,, equals 0) If the twoerror pointers P, and P, corresponding to data bytes D, and D, areturned on, then an error of a magnitude S, S, 69(1 69 T (T'' S, Q 8,) e,exists in data byte D, and an error of magnitude S 4 1 G) T"") (T S,98,) e, exists in data byte D The decoder generates data according to:

In particular, it should be recognized that the two data bytes D, and D,are recovered correctly even if multiple bits within each byte are inerror.

If two pointers, one in the data portion P, corresponding to data D,,and the P,, corresponding to C, are turned on, then an error ofmagnitude:

exits in data byte D, so that D, D',69e, represents the corrected byte.It should be noted that the check byte C, need not be corrected. If twopointers, one equal to P, corresponding to byte D, of the data and theother equal P corresponding to C, are turned on, then an error ofmagnitude S S, e, exists in byte D, so that D, D, 9e, represents thecorrected byte D,.

The apparatus for providing the error correction as previously set forthis shown in block form in the diagram of FIG. 2. The coded dataconsisting of data bytes and check bytes D' D,,...,D,, C,, C, togetherwith error pointers P P,,...,P which serve as inputs to the systemdecoder 6. The data bytes as well as the check byte C, are inputted tothe S, syndrome computer 10 where the syndrome byte S, is computedaccording to the relationship:

The data bytes and the second check byte C, are fed into the S computer12 where the second syndrome byte 8, is computed according to therelationship:

The syndrome signals S, and S actually consist of b signals since thereis an actual syndrome signal generated for each check bit in the C, andC bytes. The syndrome signals S, and 8, pass in parallel channels 14,16to the error computer 18 and control signal generator 20. The errorcomputer 18 also receives control signals I I,,...,l,, and S, and fromthe syndrome bytes S, and S computes a byte S, according to therelationship:

if, and only if, I, 1. Otherwise, S is equal to S,. If S, is equal to 1indicating signal byte correction, the error computer 18 also computes aset of control signals 1,,

7 where O s i s k-l such that I,-=1, if and only if $169 'I' S, is equalto 0. These I signals are sent to the error corrector 22 after beingORed with the I signals generated by the control signal generator 20 inOR circuits 24. The error computer 18 also receives control signals dd,,...,d and control signal J,,. The error computer computes the errorbyte e, according to the relationship:

if, and only if, d 1, otherwise S, 8;, if, and only if, Jg= 1.Otherwise, S, if j K 1 (case when none of 1,, J,,...,J,, l The 8, outputfrom the error computer 18 is also supplied to a modulo 2 adder 26 whichhas as the other input the syndrome byte 8,. The output of the modulo 2adder circuit is S, e according to the relation S 8 69 S e, which is fedto the error corrector 22. The error corrector 22 also receives the databytes D' D',,...,D',, as well as the beforementioned control signals II,,...,I and J J,,...,J These inputs and the bytes e and e, are utilizedto produce the corrected data D I ),,...,D according to the relations:

Po oGB o i The control signal generator 20 receives the syndrome bytes 8and S: from the respective S, and S, computer 10,12. In addition,pointer signals P P,,...,D are received from the pointer latch circuits28. From these inputs, the control signal generator 20 generates thefollowing signals:

1. NP I if, and only if, exactly one pointer is turned on;

2. NP I if, and only if, exactly two pointers are on;

3. N I if, and only if, zero or one pointers are on;

4. N 1 if, and only if, three or more pointers are on;

5. S I if, and only if, both syndrome bytes 8, and S; are 0;

6. S =l if, and only if, N =1 and S 0;

7. I signals giving locations of the first pointer if, and only if, 8;,=0.

8. J signals giving the location of the second pointer if, and only if,S,= 0; and

9. d signals giving the value of J-I.

l0. 8,, I if, and only it, exactly I of the syndrome bytes is non-zero;

I I. S,=S ORS S,,;

S,= I if, and only if, DATA is good;

12. N,,= I if, and only ifN I or ifS l and S =0 and none of the Isignals are active.

The distance signals d d ,...,d and the I or first pointer signals I I,...,I and the S, signal are utilized as inputs to the error computer 18for the computation of S The error computer also computes a set ofcontrol signals if S, is equal to I. These control signals I, aregenerated where 0 s I s k-l such that I, is equal to I, if, and only if,S, QBT-S is equal to 0. These I signals l sh. are sent from the errorcomputer 18 to OR circuits 24 where they are ORed with the I signals I I,...,I from the control signal generator 20. These T signals are alsosent to the control signal generator 20 indicating by the presence ofone and only one I signal that single byte correction can be done. Theresulting output of the OR circuits 24 should be I I ,...,I, which areutilized as the I signals input to the error corrector 22. the controlsignal generator 20 also produces the J signals J J ,...,J which areconnected as inputs to the error corrector 22 designating the locationof the second byte in error. I

The pointer latch circuits 28 receive as inputs pointer signals P P,...,P which are essentially error detecting signals such as paritysignals, one from each track or byte in the block of data. These pointersignals set their respective latch to its 1 condition for each bytewhich has an error. The condition of each latch is emitted by thepointer latch circuits as signals (called pointer signals) P P,,...',Pwhich serve as the pointer signals connected to the control signalgenerator 20.

The pointer signals P P,,...,P are a set of single bit signals each ofwhich are either 0 or I. P, being equal to 1 means that track I hasdetected errors and P 0 indicates that track I does not have detectederrors. The I and .I signals are derived from the pointer signals. The Isignals and J signals which serve as inputs to the error connector arederived as follows:

where I, 1, indicates that the first track in error is track i and whereJ,= 1, indicates that the second track in error is track j. In the aboveequations, the F, indicates the inverse of the function and themathematical step indicated is the AND function.

The previously mentioned distance signals d which indicate the distancebetween the J and I bytes in error, are derived from the I and J signalsas follows:

k-i 0 k-r where d, 1, indicates that the integer distance between the 2'signal and the j signal is i. It should be noted that in thedetermination of d the signal I J k is not used. I, I will be treated asa special case. It should also be noted that none of the i signals, jsignals or d signals contain a J signal. This will also be treated as aspecial case.

In operation, where two of the pointers indicate separate bytes inerror, then one I, one J and one d; will be turned on by indicating a l.The situation where only one P, indicates a l for a byte in error willbe handled as a special case. The value I is assumed in the two pointercase when none of the other .Ifs equal 1.

The operation of the invention can best be seen by consideration of anumber of different examples of error situations. The first example isthe situation where two bytes in the block of data contain errors in thedata portion D,,, D,,...,D',, of the message and two pointers areobtained indicating the bytes in error. Assuming that the bytes i and jare indicated by the pointer signals to be in error where S i j k-l.Under these conditions, the control signal generator 20 will producesignals 1, l and J, l and accordingly, d, 1 will be produced. Assumingthat the two bytes in error and that the other bytes are transcribedproperly, then the syndrome bytes S, and S, which are generated from theS, and 8, computers 10,12, respectively, will not both equal 0 since thetwo bytes are in error. Syndrome S, is algebraically equal to:

S, =e,g9e, (12) where e, represents the error pattern in byte i and 2,represents the error pattern in byte j. The second syndrome byte 8, isalgebraically equal to:

Te,@Pe,=S (13) The above-noted equations (12) and (13) can be solved fore, and e,. Multiplying equation 12) by T we get: T S =e,@T e; (14)Adding equation (12) to equation (14) we get: S T 2EB l J 15) Multiplyequation l 5) by (T 691 we get:

4=( 69 3=o (16) The byte S, is algebraically equivalent to e, It will beappreciated that the above-identified equations or steps are performedby the error computer 18. The output S, e, is utilized as one of theinputs to the modulo 2 adder circuit 26. The other input to the modulo 2adder circuit is S, which as previously mentioned, S, e,-g9e, Thus, themodulo 2 adder circuit 26 with output S is performing the function S=S,EBS =e, which is algebraically equivalent to e e lfie which isequivalent to 2,. The S5 and 8., bytes of data serve as inputs to theerror corrector 22. The error corrector 22 EXCLUSIVE ORs the receiveddata with .the derived error pattern bytes e,- and e,- to produce thecorrect data D, and 15,-. The second example is similar to the first inthat the pointers P P,,...,P,, indicate that two bytes are in error.However, one of the bytes in error is in the data portion D' ,...,D' andthe other byte in error is the first check byte C', Assume that the databyte D, has the error pattern e, and that the check byte C, contains theerror pattern e,. In this case, the control signal I, l and J, 1. Itshould be noted that 1,, l is one of the special situations mentionedpreviously and in this case, none of the distance signals d, is equal tol. The S, syndrome computer 10 producesthe syndrome byte S, which hasthe algebraic value e,6Be The S computer 12 produces the second syndromebyte S which has the algebraic value T e,. The error computer 18produces the syndrome byte 3, 7" S 998, which has the algebraic value eAccording to its definition for the case of J, l, the output of theerror computer 18 is S, S, which is equal to e,. As in example (12)given above, the modulo 2 adder circuit has as inputs S and S, andproduces as an output the byte 8, S ,6; S, where S, e, e, and S, e,.Thus, S, is equal to e, e, which is equal to e,. The error corrector 22receives S e, and the control signal I, and produces the correct databyte I)| D|(-})|.

The third example is the situation where two bytes are indicated asbeing in error by pointers P P,,...,P,, The one byte being in the dataportion D ,...,D of the message, and the second byte being the secondcheck byte C Thus, the message can be considered as having error pattern2, and C having error pattern e,. In this case, the control signal I, land none of the j signals-1,, J ,...,J are equal to 1. Accordingly, noneof the distance signals d,, d ,...,d,, are equal to l. The syndrome byteS, generated by the S, computer 10 has the algebraic value e,. Thesecond syndrome byte S, which is generated by the 8, computer 12 has thealgebraic value T e, @e,. As mentioned previously, J k l is a specialcase and the error computer 18 produces as an output S, 0. Accordingly,the modulo 2 adder 26 receives as inputs S, e, and S, 0. This circuitproduces S, e, which is utilized by the error corrector to produce 15,@691 which is the correct data byte.

The fourth example is the case where one of the syndromes S, or S, isnot 0, and either 1 or 0 pointers indicates either 1 or no bytes inerror. The signal S, 1 implies that one of the check bytes has the errorand hence the data is good. The combination of signals N S l, which isequal to 8,, controls the single byte correction. In this example, oneof the data bytes D ,...,D,, contains the error. Assuming D, has theerror pattern e,. The S, computer 10 computes the syndrome byte S, whichhas the algebraic value e,. The S, computer 12 computes the syndrome 8,which has the algebraic value T e,- =S Now, under control of signal S=1, signals T 8,358, are tested for the condition T" S, @S, 0. Thisequation will equal 0 for one and only one value of i. If it does notbecome zero, then uncorrectable multiple errors exist. The particularvalue of i for which this will be true will be 1,, since T S 9 S, T (Te,) 63s, which equals e,@e, which equals 0. The S, output is defined tobe 0. I, is then used as the correction pointer in the error corrector22 circuits to indicate which data byte Di should be EXCLUSIVE ORed withS S 658., e, to obtain the corrected data D, D,6Be,. In other words ifthe error pattern or error byte is EXCLUSIVE ORed with the received databyte that is in error, the original correct data is obtained. These Isignals are also sent to the control signal generator 20 to make thedecision as to whether or not uncorrectable errors exist.

The foregoing examples take care of all the situations which can occurthat can provide correction of the data. In the event that more than twopointers indicate r q i I15 625, .t x.r..,b9m 0 n ins e y e correction,then the control signal generator 20 will essentially put out a signalN, indicating that the data is in error and cannot be corrected.

Referring to FIG. 5, there is shown a chart indicating the geometricrelationship between the data tracks and check bit tracks. The boxeslabelled X are the data track cells or bit positions with the subscriptsindicating the geometric location. The first subscript digit indicatesthe track, while the second subscript digit indicates the location ofthe bit in the track. Note that the byte is illustrated as being 4 bitslong. Therefore, bit X01 is track 0 cell position 1. In a similarmanner, the check bits C are geometrically identified. The syndrome S,and S, from the error correction code, include an array of cells whichmay contain two errors. It

1. Apparatus for encoding a message to be sent and decoding a receivedmessage of blocks of data having k bytes of b bits each to correct anytwo bytes in error regardless of the number of bits in error within saidtwo bytes comprising: an encoder for encoding the data by adding to eachblock of data two check bytes which are related to the data inaccordance with the equation: C1 ID0 + ID1 + ID2 + ID3...IDk 1 and C2ID0 + TD1 + T2D2 +...+ Tk 1 Dk 1 respectively, wherein I is the identityelement and T, T2, T3 ...Tk 1 are distinct non-zero elements of GaloisField (2b), wherein the indicated multiplication and addition are theGalois Field defined operations, and wherein b is an integer > 1, and kis an integer 2 < k < 2b; a decoder including pointer signal receivingmeans for storing pointer signals which indicate the byte in error; saiddecoder including an error signal computing means for generating errorsignals indicative of the bits in error in each of two bytes in errorindicated by the pointer signal receiving means; and error correctingmeans utilizing said error signals from said error signal computingmeans for correcting said bytes in error.
 2. Apparatus according toclaim 1, wherein said decoder includes a first and second syndromecomputer which computes S1 and S2 syndrome signals from the block ofdata and the check bits C1 and C2 according to the equations: S1 ID''0 + ID'' 1,...ID'' k 1 + IC'' 1 S2 ID'' 0 + TD'' 1 + T2 D'' 2 + T3 D''3, . . .Tk 1 D'' 4 3 + C''2
 3. Apparatus according to claim 2, whereinsaid decoder includes a control signal generator which receives asinputs thereto said S1 and S2 syndrome signals and said pointer signalsfrom said pointer signal receiving means and generates therefrom firstbyte in error identifying signals I0, I1,...Ik; second byte in erroridentifying signals J1, J2,...,Jk and distance between first and secondbyte in error idenTifying signals d1, d2,...,dk
 1. 4. Apparatusaccording to claim 3, wherein said control signal generator furthergenerates signal N01, indicating one or no errors, signal Ng designatinguncorrectable errors exist, signal S0 indicating no errors and signal Seindicating a single byte correction should be done and in the presenceof Se, signal Sd indicating the error is in one of the check bytes andnot the data.
 5. Apparatus according to claim 3, wherein said errorsignal computing means includes modulo 2 adder circuits arranged tosolve the syndrome equation S3 T 1 S2 + S1 and AND circuits for gatingthe outputs of said modulo 2 adder circuits by the first byte in erroridentifying signal I0, I1, I2,...,Ik 1 generated by said control signalgenerator.
 6. Apparatus according to claim 5, wherein said error signalcomputing means further includes a second plurality of modulo 2 addercircuits arranged to multiply (modulo 2) syndrome S3 by (Tj i + I) 1 anda second plurality of AND circuits for gating the outputs of said secondplurality of modulo 2 adder circuits by said distance signals d toobtain the error signal S4 (Tj i + I) 1 S3 ej.
 7. Apparatus according toclaim 6, wherein an EXCLUSIVE OR circuit is provided having as one inputthereto the error signals generated by said error signal computing meansand the syndrome S1 output from said S1 syndrome computer which producesan output signal in accordance with the equation S5 S1 + S4 ei. 8.Apparatus according to claim 1, wherein said error correcting meansincludes modulo 1 adder means for adding the error computed in saiddecoder to the received data to thereby reproduce the sent data. 9.Apparatus according to claim 8, wherein said error correcting meansincludes a third plurality of AND circuits for gating the error signalsS4 ej by the J signals from the control signal generating means and theS5 ei signals from said EXCLUSIVE OR circuit by the I signals from thecontrol signal generating means and further includes a third pluralityof modulo 2 adder circuits having as inputs thereto the correspondingbit position outputs from said third plurality of AND circuits and thecorresponding data bit from the related data byte thereby adding theerrors ej and ei computed by said error signal computing means and saidEXCLUSIVE OR circuit to said received data D'' 0, D'' 1,...D'' k 1 toreproduce the sent message.
 10. Apparatus according to claim 3, whereinsaid I signals I0, I1, I2,...,Ik 1 are generated by a fourth pluralityof AND gates for gating each pointer signal P with the inverse pointersignal P of each preceding pointer signal.
 11. Apparatus according toclaim 10, wherein said J signals J1, J2,...,Jk are generated by a fifthplurality of AND gates for gating each pointer signal P with the inverseof the corresponding I signals to produce the J SIGNALS J1, J2,...,Jk.12. Apparatus according to claim 11, wherein a sixth plurality of ANDgates are provided for gating each I signal with each adjacent J signaland then each twice removed J signal increasing the distance betweensignals being gated by one signal each time until reaching the gating ofthe first I signal I0 with the last J signal Jk 1, the output of eachgroup of AND circuits being OR''ed in a second EXCLUSIVE OR circuit toproduce the distance signals d, the subscript integer representing theactual distance.